1. Field of Art
The present disclosure generally relates to the field of processor systems and related components used in such systems. In particular, the disclosure relates to reducing the overhead of translation look-aside buffers maintenance operations.
2. Description of the Related Art
Many processor or computer systems utilize cache memories to enhance compute performance. Cache memory is a memory type that is fast, limited in size, and generally located between a processor and a primary system memory. The speed of a processor in accessing data is significantly improved when the processor loads or stores data directly from the cache memory, referred to as a “hit,” instead from system memory (e.g., dynamic random access memory DRAM) that has slower transfer rates (latency). To reduce the frequency by which the processor accesses data stored in system memory, the majority of all processors maintain a subset of the data stored in system memory in cache memory. In the case when the process requests data not stored in cache memory, referred to as a “miss,” the processor retrieves the data from the system memory and accordingly updates the cache memory.
Processes executing on a processor do not distinguish between accessing cache memory or other memory, where the operating system, e.g. the kernel, is handing the scheduling, load balancing, and physical access to all the memory available on particular system architecture. To efficiently manage memory, programs are assigned to a memory location based on a virtual not physical memory space. The operating system maps virtual memory addresses used by the kernel and other programs to physical addresses of the entire memory. The virtual address space includes a range of virtual addresses available to the operating system that generally begin at an address having a lower numerical value and extend to the largest address allowed by the system architecture and is typically represented by a 32-bit address.
The translation from virtual address to physical address is stored in a section of memory called the page table. When a process requests to read data from a specific virtual address, the corresponding physical address is determined and the data from the determined physical address is retrieved. The mapping from the requested virtual address to the corresponding physical address is found in the page table of memory. Alternatively, the mapping, represented as page table entries, may be found in a local cache of the page table called the translation look-aside buffer (TLB). In some implementations, the contents of a TLB are software managed (e.g., page table entries stored in the TLB are managed by the operating system of the computing system). In other implementations, the contents of the TLB are hardware managed (e.g., page table entries stored in the TLB are managed by the processor). Software managed TLBs possess greater flexibility than hardware managed TLBs, while hardware managed TLBs operate faster than software managed TLBs. The flexibility of software managed TLBs allows the usage of the TLB with multiple memory configurations, while the speed of hardware managed TLBs allows the usage of TLBs in high performance and high speed computing systems. Therefore, there is a need for a TLB that has the flexibility of a software managed TLB, while achieving comparable performance compared to a hardware managed TLB.